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KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 1 1 product overview overview the KS57C4104/ks57c4204/ks57c4304 single-chip cmos microcontroller has been designed for very high performance using samsung's newest 4 -bit cpu core, sam4 7 ( samsung arrangeable microcontroller). with an a/d converter, led direct drive pins, an 8-bit serial i/o interface, and an 8-bit timer/coun ter, the KS57C4104/ks57c4204/ks57c4304 of fers you an ex cellent design solu tion for a wide variety of home appliance appli ca tions ? electric fans, cookers, boilers, and air conditioners, for example. up to 3 5 pins of the 42-pin sdip or 44-pin qfp package can be dedicated to i/o. seven vectored interrupts provide fast re sponse to internal and external events. in addition, the KS57C4104/ks57c4204/ks57c4304 's advanced cmos technol ogy provides for low power consumption and a wide op er ating voltage range. otp the KS57C4104/ks57c4204/ks57c4304 microcontroller is also available in otp (one time programmable) version, ks57p4104/ks57p4204/ks57p4304. ks57p4104/ks57p4204/ks57p4304 microcontroller has an on- chip 4-kbyte one-time-programmable eprom instead of masked rom. the ks57p4104/ks57p4204/ks57p4304 is comparable to KS57C4104/ks57c4204/ks57c4304, in function, in d.c. electrical characteristics and in pin configuration. development support the samsung microcontroller development system, smds, provides you with a complete pc-based develop - ment environment for ks57-series microcontrollers that is powerful, reliable, and portable. in addition to its window-based program development structure, the smds toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. the samsung generalized assembler (sama) has been designed specifically for the smds environment and accepts assembly language sources in a variety of microprocessor formats. sama generates industry-standard hex files that also contain program control data for smds compatibility.
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 2 features summary memory ? 256 4-bit ram ? 4,096 8-bit rom 3 5 i/o pins ? i/o: 31 pins including 8 led direct drive pins (KS57C4104/c4304) 18 pins including 8 led direct drive pins (ks57c4204) ? input only: 4 pins a/d converter ? 6 -channel with 8-bit resolution ? 22 . 8 9 s conversion speed at 4.19 mhz basic timer ? one 8-bit basic timer ? watchdog timer functions ? four interval clock selection timer/counter s ? two 8-bit timer/counter (tc0, tc1) ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? pwm output mode (tc1) watch timer ? one watch timer 8-bit ? time interval generation: 0.5 s, 3.9 ms at 4.19 mhz ? four frequency outputs to buz pin 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable ? internal or external clock source built-in reset circuit (ks57c4304 only) ? built-in power-on reset circuit interrupts ? f ive internal vectored interrupts (intb, intt0, intt1, ints, intad) ? three external vectored interrupts (int0, int1, int4) ? two quasi-interrupts (int2, intw) bit sequential carrier ? supports 16-bit serial data transfer in arbitrary format memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (system oscillation stops) oscillation sources ? crystal, ceramic, or rc for system clock ? crystal, ceramic: 0 . 4?6.0 mhz ? rc: 4 mhz ( typ) ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0. 9 5, 1.91, 15.3 s at 4.19 mhz ? 0.67, 1.33, 10.7 s at 6.0 mhz operating temperature ? ? 40 c to 85 c operating voltage range ? 1 . 8 v to 5 . 5 v (KS57C4104/c4204) ? 2.5 v to 5.5 v (ks57c4304) package type ? 42-pin sdip , 44-pin qfp (KS57C4104/c4304) 30-pin sdip, 28-pin sop (ks57c4204)
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 1 14 electrical data overview in this section, information on ks 57c4104/c4204/c4304 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? operating voltage range ? a.c. electrical characteristics ? a/d c onverter e lectrical c haracteristics ? i/o capacitance stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a.c timing measurement point s (except for x in ) ? clock timing measurement at x in ? tcl0 /1 timing ? input timing for reset signal ? input timing for external interrupts and quasi-interrupts ? ks57c4304 power-on reset timing ? serial data transfer timing
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 2 table 14 - 1. KS57C4104/c4204 absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6 . 5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one pin ? 15 ma all output pins ? 35 output current low i ol one pin peak value (note) + 30 ma rms value + 15 all pins peak value (note) + 100 rms value + 60 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty .
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 3 table 14 - 2. KS57C4104/c4204 d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6 and reset 0.8 v dd v dd v ih3 x in, x out v dd ? 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6 and reset 0.2 v dd v il3 x in, x out 0. 1 output high voltage v oh v dd = 4.5 v to 5 . 5 v i oh = ? 1 ma ports 0, 2?8 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5 . 5 v i ol = 15 ma ports 4 and 5 only ? 0.4 2 v i ol = 4 ma all output ports except ports 4 and 5 0.2 input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in and x out only 20 input low leakage current i lil1 v i = 0 v all input pins except x in and x out , reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-u p resistor r l1 v i = 0 v; v dd = 5 v except reset 25 50 100 k w v i = 0 v; v dd = 3 v except reset 50 100 200 pull-u p resistor r l2 v i = 0 v; v dd = 5 v ; reset 100 250 400 k w v i = 0 v; v dd = 3 v ; reset 200 500 800
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 4 table 14 - 2. KS57C4104/c4204 d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.3 5.5 v dd = 3 v 10% 6.0mhz 1.4 4.0 4.19mhz 1.1 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 1.1 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 1.0 1.8 v dd = 3 v 10% 6.0mhz 0.5 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.1 5.0 m a stop mode; v dd = 3.0 v 1 0% 0.1 3.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and adc. 2. the supply current assumes a cpu clock of fx/4.
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 5 table 14 -3 . KS57C4104/c4204 system clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 v dd = 1.8 v to 5.5 v 0.4 ? 3.0 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator xin xout r oscillation frequency limitation v dd = 5 v r = 8.2 k w ? 4 ? mhz notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 6 cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.6 khz cpu clock 1.5 mhz 4.2 mhz main oscillator frequency (divided by 4) 6 mhz 1 2 3 4 5 6 2.7 5 .5 0 .75 mhz 1 .8 3 mhz figure 14 -1 . KS57C4104/c4204 standard operating voltage range table 14-4 . KS57C4104/c4204 a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s time v dd = 1.8 v to 5.5 v 1.33 tcl0 /1 input f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz frequency v dd = 1.8 v to 5.5 v 0.75 mhz tcl0 /1 input high , t tih , t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s low width v dd = 1.8 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 7 table 14-4 . KS57C4104/c4204 a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units sck high, low width t kh , t kl v dd = 2 . 7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy /2 ? 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to sck high t sik v dd = 2 . 7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 1.8 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2 . 7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 1.8 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2 . 7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 ( 2) ? ? m s int1, int2, int4, ks0 ?ks3 10 reset input low width t rsl input 10 ? ? m s note s : 1. r(1k w ) and c (100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 8 table 14 -5 . ks57c4304 absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6 . 5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one pin ? 15 ma all output pins ? 35 output current low i ol one pin peak value (note) + 30 ma rms value + 15 all pins peak value (note) + 100 rms value + 60 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty .
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 9 table 14 -6 . ks57c4304 d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6 and reset 0.8 v dd v dd v ih3 x in, x out v dd ? 0 . 1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6 and reset 0.2 v dd v il3 x in, x out 0.1 output high voltage v oh v dd = 4.5 v to 5 . 5 v i oh = ? 1 ma ports 0, 2?8 v dd ? 1.0 ? ? v output low voltage v ol v dd = 3.5 v i ol = 15 ma ports 4 and 5 only ? 0.4 2 v i ol = 4 ma all output ports except ports 4 and 5 0.2 input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in and x out only 20 input low leakage current i lil1 v i = 0 v all input pins except x in and x out, reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-up resistor r l1 v i = 0 v; v dd = 5 v except reset 25 50 100 k w v i = 0 v; v dd = 3 v except reset 50 100 200 pull-up resistor r l2 v i = 0 v; v dd = 5 v ; reset 100 250 400 k w v i = 0 v; v dd = 3 v ; reset 200 500 800
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 10 table 14 -6 . ks57c4304 d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.1 8.0 ma current (1) crystal oscillator; c1 = c2 = 22pf 4.19mhz 2.4 5.5 v dd = 3 v 10% 6.0mhz 1.5 4.0 4.19mhz 1.2 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 1.2 2.5 ma crystal oscillator; c1 = c2 = 22pf 4.19mhz 1.1 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.5 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 120 200 m a stop mode; v dd = 3.0 v 1 0% 100 150 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and adc. 2. the supply current assumes a cpu clock of fx/4. table 14 -7 . ks57c4304 power-on reset circuit characteristics (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) parameter symbol conditions min typ max units power-on reset voltage high v dd h 2.5 5.5 v power-on reset voltage low v dd l 0 2.0 2.2 v power supply voltage rise time t r 10 (1) us power supply voltage off time t off 0.5 s power-on reset circuit i dd pr v dd = 5 v 10% 120 200 ua cunsumption current (2) v dd = 3 v 10% 100 150 ua notes: 1. 2 17 / fx (= 31.3 ms at fx = 4.19 mhz) 2. current consumed when power-on reset circuit is p rovided internally.
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 11 table 14 -8 . ks57c4304 system clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.5 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.5 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.5 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator xin xout r oscillation frequency limitation v dd = 5 v r = 8.2 k w ? 4 ? mhz notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 12 cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.6 khz cpu clock 1.5 mhz 4.2 mhz main oscillator frequency (divided by 4) 6 mhz 1 2 3 4 5 6 2.7 5 .5 0 .75 mhz 1 .8 3 mhz 2.5 figure 14 -2 . ks57c4304 standard operating voltage range
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 13 table 14 -9 . ks57c4304 a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5 .5 v 0. 67 ? 64 s tcl0 /1 input frequency f ti0 v dd = 2.7 v to 5 .5 v 0 ? 1 .5 mhz tcl0 /1 input high, low width t tih0 , t til0 v dd = 2.7 v to 5 .5 v 0.48 ? ? s sck cycle time t kcy v dd = 2.7 v to 5 .5 v external sck source 800 ? ? ns internal sck source 670 sck high, low width t kh , t kl v dd = 2.7 v to 5 .5 v external sck source 325 ? ? ns internal sck source t kcy / 2 ? 50 si setup time to sck high t sik v dd = 2.7 v to 5 .5 v external sck source 100 ? ? ns internal sck source 150 si hold time to sck high t ksi v dd = 2.7 v to 5 .5 v external sck source 400 ? ? ns internal sck source 400 output delay for sck to so t kso v dd = 2.7 v to 5 .5 v external sck source ? ? 300 ns internal sck source 250 interrupt input t inth , int0 (note) ? ? s high, low width t intl int1, int2, int4, ks0? ks3 10 reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 14 table 14 -10 . a/d converter electrical characteristics (t a = ? 10 c to + 70 c, v dd = 3.5 v to 5 . 5 v, v ss = av ss = 0 v) parameter symbol condition min typ max units resolution ? ? 8 8 8 bit absolute accuracy (1) ? 2.5 v < av ref < v dd ? ? 1.5 lsb conversion time (2) t con ? ? 96 /fx (3) ? s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? ? 1000 ? m w notes : 1. absolute accuracy does not include the quantization error ( 1/2 lsb). 2. conversion time is the time required from the moment a conversion operation starts until it ends (eoc = 0). 3. ' fx' is the abbreviation for system clock. table 14 -11 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 14 -12 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr ? ? 0.1 10 a release signal set time t srel ? 0 ? ? ms oscillation stabilization time (1) t wait when released by reset ? 2 17 / fx ? ms when released by interrupt ? (2) ? ms notes: 1. during oscillation stabilization time, cpu opera tion must be stopped to avoid unstable operation upon oscillation start. 2. the basic timer causes a delay of 2 17 / fx after a reset.
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 15 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode ~ ~ ~ ~ figure 14 -3 . stop mode release timing when initiated by reset v dd execution of stop instruction v dddr data retention stop mode t wait t srel idle mode normal operating mode power-down mode terminating (interrupt request) ~ ~ ~ ~ figure 14 -4 . stop mode release timing when initiated by interrupt request
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 16 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14 -5 . a.c. timing measurement points (except for x in ) x in t xl t xh 1 / f x v dd ? 0.5 v 0.4 v figure 14 -6 . clock timing measurement at x in tcl0 t til0 t tih0 0.8 v dd 0.2 v dd 1 / f ti0 figure 14 -7 . tcl0 /1 timing
KS57C4104/p4104/c4204/p4204/c4304/p4304 electrical data 14- 17 reset 0.2 v dd t rsl figure 14 -8 . input timing for reset signal int0, 1, 2, 4 ks0 to ks3 t intl t inth 0.8 v dd 0.2 v dd figure 14 -9 . input timing for external interrupts and quasi-interrupts
electrical data KS57C4104/p4104/c4204/p4204/c4304/p4304 14- 18 v dd t off t r v ddh v ddl figure 14 -10 . ks57c4304 power-on reset timing sck t kl t kh t kcy 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t kso t sik t ksi figure 14 -11 . serial data transfer timing
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 3 table 1 - 1. comparision table feature KS57C4104 ks57c4204 ks57c4304 core sam47 sam47 sam47 rom 4 k bytes same same ram 256 nibbles same same i/o 35 (4 input only) 21 (3 input only) 35 (4 input only) por (1) none none built in/ typ: 2.0 v sio 8-bit sio x 1 same same timer0 8-bit timer/counter same same timer1(pwm) 8-bit timer/counter (8-bit pwm x 1) same same watchdog timer watch-dog 4 selectable interval same same adc 8-bit x 6 8-bit x 4 8-bit x 6 av ss none (2) same same interrupt external x 3 internal x 5 quasi x 2 (ks0?ks3) external x 2 internal x 5 quasi x 1 ( ? ) external x 3 internal x 5 quasi x 2 (ks0?ks3) power down stop/idle same same oscillator crystal, ceramic, rc same same operating frequency 0.4?6 mhz same same operating voltage 1.8?5.5 v 1.8?5.5 v 2.5?5.5 v otp/mtp otp same same package 42sdip/44qfp 30sdip/28sop 42sdip/44qfp notes 1. por (power on reset)/ typ 2.0 v low voltage detector. 2. internal a/d converter ground (bonded to v ss internally)
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 4 block diagram arithmetic and logic unit interrupt control block instruction register program counter program status word 256 x 4-bit data memory 8-bit timer/ counter 0 stack pointer instruction decoder clock reset x in x out internal interrupts 4 k byte program memory int0, int1, int2,int4 ba s ic timer watch timer p0.0/ sck p0.1/so p0.2/si p0.3/buz p3.0/ad4 p3.1/ad5 p3.2/clo/tcl1 p3.3/pwm / tclo1 p4.0-4.3 p5.0-5.3 i/o port 4 i/o port 5 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 i/o port 6 p7.0-7.3 i/o port 7 p8.0/tcl0 p8.1/tclo0 p8.2 i/o port 8 i/o port 3 p2.0-p2.3/ ad0-ad3 i/o port 2 serial i/o i/o port 0 i/o port 2 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 input port 1 a/d converter av ref 8-bit timer/ counter 1 figure 1 -1 . KS57C4104/c4204/c4304 simplified block diagram
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 5 pin assignments p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p3.0/ad4 p3.1/ad5 av ref p3.2/clo/tcl1 p3.3/pwm/tclo1 p4.0 v dd v ss x out x in test p4.1 p4.2 reset p4.3 p5.0 p5.1 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si p0.1/so p0.0/ sck p5.3 p5.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 KS57C4104 42 sdip 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1 -2 . KS57C4104 pin assignment (42-sdip)
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 6 1 2 3 4 5 6 7 8 9 10 11 KS57C4104 44 qfp reset p4.3 p 5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so p0.2/si p0.3/buz nc 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 33 32 31 30 29 28 27 26 25 24 23 4 4 43 42 41 40 3 9 38 37 36 35 34 nc p3.1/ad5 p3.0/ad4 p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 av ref p3.2/clo/tcl1 p3.3/pwm/tclo1 p4.0 v dd v ss x out x in test p4.1 p4.2 figure 1 -3 . KS57C4104 pin assignment (44-qfp)
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 7 v ss x out x in test p4.1 p4.2 reset nc p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so v dd p4.0 p3.3/pwm/tclo1 p3.2/clo/tcl1 av ref nc p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ks57c4204 30 sdip 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 figure 1 -4 . ks57c4204 pin assignment (30-sdip)
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 8 v ss x out x in test p4.1 p4.2 reset p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so v dd p4.0 p3.3/pwm/tclo1 p3.2/clo/tcl1 av ref p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ks57c4204 28 sop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 figure 1 -5 . ks57c4204 pin assignment (28-sop)
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 9 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p3.0/ad4 p3.1/ad5 av ref p3.2/clo/tcl1 p3.3/pwm/tclo1 p4.0 v dd v ss x out x in test p4.1 p4.2 reset p4.3 p5.0 p5.1 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si p0.1/so p0.0/ sck p5.3 p5.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ks57c4304 42 sdip 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1 -6 . ks57c4304 pin assignment (42-sdip)
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 10 1 2 3 4 5 6 7 8 9 10 11 ks57c4304 44 qfp reset p4.3 p 5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so p0.2/si p0.3/buz nc 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 33 32 31 30 29 28 27 26 25 24 23 4 4 43 42 41 40 3 9 38 37 36 35 34 nc p3.1/ad5 p3.0/ad4 p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 av ref p3.2/clo/tcl1 p3.3/pwm/tclo1 p4.0 v dd v ss x out x in test p4.1 p4.2 figure 1 -7 . ks57c4304 pin assignment (44-qfp)
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 11 pin descriptions table 1 -2 . KS57C4104/c4304 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 24 (18) 25 ( 19 ) 2 6 (2 0 ) 2 7 (2 1 ) sck so si b uz p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are individually assignable by software to pins p1.0, p1.1, and p1.2. 2 8 (2 3 ) 2 9 (2 4 ) 30 ( 25 ) 31 ( 26 ) int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. n-channel open-drain output. 1-bit or 4-bit write and test is possible. individual pins are software configurable as ad input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 1 (38) 2 (39) 3 (40) 4 (4 1 ) ad0 ad1 ad2 ad3 p3.0 p3.1 p3.2 p3.3 i/o same as port 0 (p0.0?p0.3) 5 (42) 6 (43) 8 (2) 9 (3) ad4 ad5 clo/tcl1 pwm/tclo1 p4.0 p4.1 p4.2 p4.3 p5.0?p5.3 i/o 4-bit i/o ports. ports 4 and 5 can be configured individually as n- channel open-drain or as cmos push-pull output by software. 1-bit and 4-bit read/write and test is possible. ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 10 (4) 16 (10) 17 (11) 19 (13) 20?23 (14?17) ? p6.0 ? p6.3 p7.0?p7.3 p8.0 p8.1 p8.2 i/o same as port 0 except port 8 is a 3 -bit i/o port 32?35 (27?30) 36?39 (31?34) 40 (35) 41 (36) 42 (37) ks0 ?ks3 ? tcl0 tclo0 ?
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 12 table 1 -2 . KS57C4104/c4304 pin descriptions (continued) pin name pin type description number share pin sck i/o serial i/o interface clock signal 24 ( 18 ) p0.0 so i/o serial data output 25 ( 19 ) p0.1 si i/o serial data input 2 6 (2 0 ) p0.2 buz i/o 2 khz, 4khz, 8khz, or 16 khz frequency output at the watch timer clock frequency of 32.768 khz 2 7 ( 21 ) p0.3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 2 8? 2 9 (2 3? 2 4 ) p1.0, p1.1 int2 i quasi-interrupt input with rising edge detection 30 (2 5 ) p1.2 int4 i external interrupts with detection of rising and falling edges 31 (2 6 ) p1.3 ad0?ad3 ad4?ad5 i/o a/d converter analog inputs 1?4 ( 3 8 ? 41 ) 5?6 (42?43) p2.0?p2.3 p3.0?p3.1 tcl0 i/o external clock input for timer/counter 0 40 (35 ) p 8 .0 tclo0 i/o timer/counter clock output 41 (3 6 ) p 8 .1 clo i/o clock output 8 ( 2 ) p 3 .2 tcl1 i/o external clock input for timer/counter1 8 (2) p 3 .2 pwm i/o pwm output 9 (3) p 3 . 3 tclo1 i/o timer/counter clock output1 9 (3) p 3 . 3 ks0? ks3 i/o quasi-interrupt input with falling edge detection 32 ? 3 5 (2 7? 30 ) p6.0?p6. 3 v dd ? main power supply 11 ( 5 ) ? v ss ? ground 12 ( 6 ) ? reset i reset signal 18 ( 12 ) ? x in , x out ? crystal, ceramic, or rc oscillator signal for system clock. 1 4, 13 ( 8 , 7 ) ? av ref ? a/d converter analog reference voltage 7 ( 1 ) ? test i test signal input (must be connected to v ss ) 15 ( 9 ) ? nc ? no connection (no bonding pin) ( 22, 44 ) ? note: parentheses indicate 44-qfp pin number.
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 13 table 1 -3 . ks57c4204 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 14 ( 13 ) 15 ( 14 ) 16 ( 15 ) 17 ( 16 ) sck so si b uz p1.0 p1.1 p1.2 i 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are individually assignable by software to pins p1.0, p1.1, and p1.2. 18 ( 17) 19 ( 18 ) 20 ( 19) int0 int1 int2 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. n-channel open-drain output. 1-bit or 4-bit write and test is possible. individual pins are software configurable as ad input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 21 (20) 22 (21) 23 (22) 24 (23 ) ad0 ad1 ad2 ad3 p3.2 p3.3 i/o same as port 0 (p0.0?p0.3) 27 (25) 28 ( 26 ) clo/tcl1 pwm/tclo1 p4.0 p4.1 p4.2 p4.3 p5.0?p5.3 i/o 4-bit i/o ports. ports 4 and 5 can be configured individually as n- channel open-drain or as cmos push-pull output by software. 1-bit and 4-bit read/write and test is possible. ports 4 and 5 can be paired to enable 8-bit data transfer. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 29 (27) 5 (5) 6 (6) 9 (8) 10?13 (9?12) ?
product overview KS57C4104/p4104/c4204/p4204/c4304/p4304 1- 14 table 1 -3 . ks57c4204 pin descriptions (continued) pin name pin type description number share pin sck i/o serial i/o interface clock signal 14 ( 13 ) p0.0 so i/o serial data output 15 ( 14 ) p0.1 si i/o serial data input 16 ( 15 ) p0.2 buz i/o 2 khz, 4khz, 8khz, or 16 khz frequency output at the watch timer clock frequency of 32.768 khz 17 ( 16 ) p0.3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 18, 19 ( 17, 18 ) p1.0, p1.1 int2 i quasi-interrupt input with rising edge detection 20 ( 19 ) p1.2 ad0?ad3 i/o a/d converter analog inputs 21 ? 24 (20 ? 23 ) p2.0?p2.3 clo i/o clock output 27 ( 25 ) p 3 .2 tcl1 i/o external clock input for timer/counter1 27 (25) p 3 .2 pwm i/o pwm output 28 (26) p 3 . 3 tclo1 i/o timer/counter clock output1 28 (26) p 3 . 3 v dd ? main power supply 30 ( 28 ) ? v ss ? ground 1 ( 1 ) ? reset i reset signal 7 ( 7 ) ? x in , x out ? crystal, ceramic, or rc oscillator signal for system clock. 3 , 2 ( 3 , 2 ) ? av ref ? internal a/d converter analog reference voltage 26 (24) ? test i test signal input (must be connected to v ss ) 4 ( 4 ) ? nc ? no connection (no bonding pin) 8, 25 ? note: parentheses indicate 28-sop pin number.
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 15 table 1 -4 . overview of KS57C4104/c4204/c4304 pin data pin names share pins i/o type reset value circuit type p0.0?p0.3 sck , so, si, b uz i/o input type d p1.0 p1.1 p1.2 int0 (note) int1 (note) int2 (note) i input type a-1 p1.3 int4 i input type a p2.0?p2.3 ad0?ad3 i/o ad i nput type f-3 p3.0 p3.1 p3.2 p3.3 ad4 ad5 clo/tcl1 tclo1/pwm i/o input type f type f type d type d p4.0?p4.3 p5.0?p5.3 ? i/o input type e p6.0 p6.1 p6.2 p6.3 ks0 (note) ks1 (note) ks2 (note) ks3 (note) i/o input type d p7.0?p7.3 ? i/o input type d p8.0 p8.1 p8.2 tcl0 (note) tclo0 ? i/o input type d v dd , v ss ? ? ? ? x in , x out ? ? ? ? reset ? i ? type b-2 (note) av ref ? ? ? ? test ? i ? ? nc ? ? ? ? note: a noise filter circuit is built-in.
product overview KS57C4104/p4104/c4204/p4204 microcontroller (p reliminary s pec ) 1- 16 pin circuit diagrams v dd p - channel in n - channel figure 1 -8 . pin circuit type a pull-up resistor enable circuit type a in v dd figure 1 -9 . pin circuit type a-1 v dd reset 1m w 7pf figure 1 -10 . pin circuit type b-2 data output disable out v dd p - channel n - channel figure 1 -11 . pin circuit type c
KS57C4104/p4104/c4204/p4204/c4304/p4304 product overview 1 - 17 pull-up resistor enable data output disable circuit type a i/o v dd circuit type c figure 1 -12 . pin circuit type d input v dd data output disable pne pull-up resistor enable v dd in/out figure 1 -13. pin circuit type e in/out v dd circuit type c data data output disable pull-up resistor enable to adc adc input select figure 1 -14. pin circuit type f v dd data output disable in/out data to adc pull-up resistor enable adc input select figure 1 -15. pin circuit type f-3
product overview KS57C4104/p4104/c4204/p4204 microcontroller (p reliminary s pec ) 1- 18 notes
KS57C4104/p4104/c4204/p4204/c4304/p4304 (p reliminary s pec ) mechanical data 15- 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram note : dimensions are in millimeters. 0-15 15.24 0.25 +0.1 ? 0.05 0.51min 3.30 0.3 5.08max 1.00 0.1 0.50 0.1 (1.77) 1.778 3.50 0.2 39.10 0.2 39.50 max 42-sdip-600 14.00 0.2 #1 #21 #42 #22 figure 15 - 1. 42-sdip-600 package dimensions
mechanical data KS57C4104/p4104/c4204/p4204/c4304/p4304 (p reliminary s pec ) 15- 2 note : dimensions are in millimeters. 44-qfp-1010 13.20 0.3 #44 (1.00) #1 13.20 0.3 10.00 0.2 0.35 +0.10 - 0.05 0.10 max 0.15 +0.10 - 0.05 0-8 0.05 min 2.05 0.10 2.30 max 0.80 0.20 0.80 10.00 0.2 figure 15 - 2. 44-qfp-1 0 1 0 package dimensions
KS57C4104/p4104/c4204/p4204/c4304/p4304 (p reliminary s pec ) mechanical data 15- 3 note : dimensions are in millimeters. 30-sdip-400 8.94 0.2 #1 #15 #30 #16 0-15 0.25 +0.1 ? 0.05 10.16 1.12 0.1 0.51min 3.81 0.2 3.30 0.3 5.08max (1.30) 0.56 0.1 27.48 0.2 27.88 max 1.778 figure 15 - 3. 30-sdip-400 package dimensions
mechanical data KS57C4104/p4104/c4204/p4204/c4304/p4304 (p reliminary s pec ) 15- 4 note : dimensions are in millimeters. 7.70 0.2 0-8 0.60 0.20 9.53 0.15 +0.10 - 0.05 28-sop-375 10.45 0.3 #1 #14 #28 #15 0.10 max 0.05min 2.15 0.2 2.55max 17.62 0.2 18.02 max (0.56) 0.41 0.1 1.27 figure 15 -4 . 28-sop-375 package dimensions
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 1 16 ks57p4104/p4204/p4304 otp overview the ks57p4104/p4204/p4304 single-chip cmos microcontroller is the otp (one time programmable) version of the KS57C4104/c4204/c4304 microcontroller. it has an on-chip otp rom instead of masked rom. samsung s own serial protocol used for otp program pin information regarding otp program can be referred otp pin description. the ks57p4104/p4204/p4304 is fully compatible with the KS57C4104/c4204/c4304, in function, in d.c. electrical characteristics and in pin configuration. because of its simple programming requirements, the ks57p4104/p4204/p4304 is ideal for use as an evaluation chip for the KS57C4104/c4204/c4304.
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 2 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p3.0/ad4 p3.1/ad5 av ref p3.2/clo/tcl1 sdat /p3.3/pwm/tclo1 sclk /p4.0 v dd / v dd v ss / v ss x out x in v pp /test p4.1 p4.2 reset / reset p4.3 p5.0 p5.1 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si p0.1/so p0.0/sckb p5.3 p5.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ks57p4104 42 sdip 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 16-1. ks57p4104 pin assignments (42-sdip)
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 3 1 2 3 4 5 6 7 8 9 10 11 ks57p4104 44 qfp reset /reset p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so p0.2/si p0.3/buz nc 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 33 32 31 30 29 28 27 26 25 24 23 4 4 43 42 41 40 3 9 38 37 36 35 34 nc p3.1/ad5 p3.0/ad4 p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 av ref p3.2/clo/tcl1 sdat / p3.3/pwm/tclo1 sclk /p4.0 v dd / v dd v ss / v ss x out x in v pp /test p4.1 p4.2 note: the bolds indicate an otp pin name. figure 16-2. ks57p4104 pin assignments (44-qfp)
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 4 v ss / v ss x out x in v pp /test p4.1 p4.2 reset / reset nc p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so v dd/ v dd p4.0/ sclk p3.3/pwm/tclo1/ sdat p3.2/clo/tcl1 av ref nc p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ks57p4204 30 sdip 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 note: the bolds indicate an otp pin name. figure 16-3. ks57p4204 pin assignments (30-sdip)
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 5 v ss /v ss x out x in v pp /test p4.1 p4.2 reset / reset p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so v dd/ v dd p4.0/ sclk p3.3/pwm/tclo1/ sdat p3.2/clo/tcl1 av ref p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ks57p4204 28 sop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 note: the bolds indicate an otp pin name. figure 16-4. ks57p4204 pin assignments (28-sop)
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 6 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p3.0/ad4 p3.1/ad5 av ref p3.2/clo/tcl1 sdat /p3.3/pwm/tclo1 sclk /p4.0 v dd / v dd v ss / v ss x out x in v pp /test p4.1 p4.2 reset / reset p4.3 p5.0 p5.1 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz p0.2/si p0.1/so p0.0/sckb p5.3 p5.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ks57p4304 42 sdip 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 16-5. ks57p4304 pin assignments (42-sdip)
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 7 1 2 3 4 5 6 7 8 9 10 11 ks57p4304 44 qfp reset /reset p4.3 p5.0 p5.1 p5.2 p5.3 p0.0/ sck p0.1/so p0.2/si p0.3/buz nc 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 20 21 22 p7.2 p7.1 p7.0 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 33 32 31 30 29 28 27 26 25 24 23 4 4 43 42 41 40 3 9 38 37 36 35 34 nc p3.1/ad5 p3.0/ad4 p2.3/ad3 p2.2/ad2 p2.1/ad1 p2.0/ad0 p8.2 p8.1/tclo0 p8.0/tcl0 p7.3 av ref p3.2/clo/tcl1 sdat / p3.3/pwm/tclo1 sclk /p4.0 v dd / v dd v ss / v ss x out x in v pp /test p4.1 p4.2 note: the bolds indicate an otp pin name. figure 16-6. ks57p4304 pin assignments (44-qfp)
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 8 table 16-1. pin descriptions of ks57p4104/p4304 used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.3 sdat 9 (3) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p4.0 sclk 10 (4) i/o serial clock pin. input only pin. test v pp (test) 15 (9) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 18 (12) i chip initialization v dd /v ss v dd /v ss 11/12 (5/6) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate 44-qfp pin number. table 16-2. pin descriptions of ks57p4204 used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.3 sdat 28 (26) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p4.0 sclk 29 (27) i/o serial clock pin. input only pin. test v pp (test) 4 (4) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 (7) i chip initialization v dd /v ss v dd /v ss 30/1 (28/1) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate 28-sop pin number.
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 9 table 16-3. comparison of ks57p4104/p4204 and KS57C4104/c4204 features characteristic ks57p4104/p4204 KS57C4104/c4204 program memory 4 k byte eprom 4 k byte mask rom operating voltage (v dd ) 1.8 v to 5 . 5 v 1.8 v to 5 . 5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42 sdip, 44 qfp, 30 sdip, 28 sop 42 sdip, 44 qfp, 30 sdip, 28 sop eprom programmability user program 1 time programmed at the factory table 16-4. comparison of ks57p4304 and ks57c4304 features characteristic ks57p4304 ks57c4304 program memory 4 k byte eprom 4 k byte mask rom operating voltage (v dd ) 2.5 v to 5 . 5 v 2.5 v to 5 . 5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42 sdip, 44 qfp 42 sdip, 44 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the ks57p4104/p4204/p4304, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-4 below. table 16-5. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 10 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16-7. otp programming algorithm
KS57C4104/p4104/c4204/p4204/c4304/p4304 ks57p4104/p42 04/p4304 otp 16- 11 table 1 6 - 6 . ks57p4104/p4204 d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.3 5.5 v dd = 3 v 10% 6.0mhz 1.4 4.0 4.19mhz 1.1 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 1.1 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 1.0 1.8 v dd = 3 v 10% 6.0mhz 0.5 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.1 5.0 m a stop mode; v dd = 3.0 v 1 0% 0.1 3.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and adc. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.6 khz cpu clock 1.5 mhz 4.2 mhz main oscillator frequency (divided by 4) 6 mhz 1 2 3 4 5 6 2.7 5 .5 0 .75 mhz 1 .8 3 mhz figure 1 6-8 . ks57p4104/p4204 standard operating voltage range
ks57p4104/p4204/p4304 otp KS57C4104/p410 4/c4204/p4204/c4304/p4304 16- 12 table 1 6-7 . ks57p4304 d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.5 v to 5 . 5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.1 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.4 5.5 v dd = 3 v 10% 6.0mhz 1.5 4.0 4.19mhz 1.2 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 1.2 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 1.1 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.5 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 120 200 m a stop mode; v dd = 3.0 v 1 0% 100 150 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and adc. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.6 khz cpu clock 1.5 mhz 4.2 mhz main oscillator frequency (divided by 4) 6 mhz 1 2 3 4 5 6 2.5 5 .5 figure 1 6-9 . ks57p4304 standard operating voltage range

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